China has been fenced out of the two hardest technologies in computing: EUV lithography — the machines that print the world's most advanced chips — and HBM, the stacked memory every AI accelerator needs. This is a teardown, not a lecture: piece by piece, name by name, patent by patent — what each wall is made of, who holds each key, what China can and cannot buy, and how long the fence plausibly holds.
The thesis under test: once China catches up on both, its integrated ecosystem — state capital, a full equipment bench, the world's largest chip market and open AI models, all in one jurisdiction — becomes unparalleled. Every claim is graded: HARD REPORTED ANALYST MODEL COMPANY CLAIM FORUM SPECULATION
Definition: China supplies Ascend-class demand at usable volume and acceptable cost with no Western, Japanese or Korean HBM, base-die, bonding, packaging-material or tester input.
Definition: high-volume, commercially usable patterning of leading-edge logic on a fully domestic tool — no ASML, Zeiss, TRUMPF, Cymer or Japanese input. A first prototype or first chip does not stop this clock.
Definition: the later of the two clocks. On this date China is no longer bound at all by the Western stack for EUV lithography and HBM — and the integrated-ecosystem thesis becomes testable.
Confidence: Low (HBM) and Low (EUV) — these are ANALYST MODEL syntheses, not forecasts of record. What moves them ±2 years, and the signposts to watch, are in the roadmap and the timeline.
Each clock is checked daily against the indicators below (dossier §15). A clock moves only when evidence against one of these indicators warrants it — and every move is logged in the changelog under the panels, with its reason.
Every change to a clock date, in chronological order, with the evidence that caused it. The clock values themselves live in one data block at the top of this page — a daily update changes a date in exactly one place.
Why these two walls, specifically? Because almost everything else in the stack — etch, deposition, cleaning, design software, mature-node fabs — China has already substituted or is substituting at measurable rates. EUV and HBM are where substitution has not yet happened. If both fall, what remains is not a copy of the Western chain but a structurally different one.
Verdict of the evidence: the thesis is directionally supported on HBM — the clock is running and the wall is visibly cracking — and unproven on EUV, where the honest statement is a prototype that generates EUV light but has produced no working chips. Everything below is the evidence, piece by piece, so you can grade it yourself.
An ASML TWINSCAN NXE is not one invention; it is a network of individual monopolies bolted together. EUV light (13.5nm) is absorbed by glass and by air, so the whole optical path is mirrors, in vacuum. A tin droplet is shot 50,000 times a second, the plasma it makes is gathered by a collector mirror, shaped onto a reflective mask, then demagnified through a stack of mirrors so perfect that across ~11 reflections under 2% of the light survives. Click any numbered part to get its monopolist, the physics that makes it hard, China's challenger, and the roadmap for that single piece.
2025 net sales €32.7bn; EUV sales €11.6bn on 48 systems (44 NXE ≈ €237m each on average; 4 EXE ≈ €289m). The installed-base business — service, spares, upgrades — was €8.2bn (+26%): the service annuity is itself a lock-in key, because a tool you cannot service is a tool you cannot run. H1 2026: 29 NXE, 3 EXE shipped. ASML's own binding constraint has reportedly migrated to metrology systems, optical-column parts and precision vacuum chambers.
China was 41% of ASML net system sales in 2024 and 33% in 2025, guided to ~20% for 2026 — the DUV stockpile unwinding in real time.
A prototype completed in early 2025 in a secure Shenzhen lab — team including former ASML engineers working under aliases, built partly by reverse-engineering with parts from older ASML machines bought on secondary markets — generates EUV light but has produced no working chips. The programme runs ~6 years, is overseen by Ding Xuexiang and coordinated in practice by Huawei; talent bonuses of ¥3–5m ($420k–$700k) plus housing are reported. Government target: chips by 2028; participants quoted call 2030 more realistic. Hardest hurdle named: precision optics.
Corroborated via TrendForce (18 Dec 2025) and CACM; the Reuters article text was not directly retrieved in this research run — grade held at REPORTED.
HBM is memory stood on end: DRAM dies pierced by through-silicon vias (TSVs), thinned to tens of microns, and stacked 4, 8, 12 or 16 high on a logic base die, then placed beside the processor on a silicon interposer. The catch is arithmetic: if every layer must survive, yields multiply. Move the sliders and see why a stack that sounds easy is a volume business only three companies on earth can run.
MR-MUF (SK hynix): stack the dies, mass-reflow them together, then inject liquid epoxy moulded underfill — better heat dissipation, and the process behind SK hynix's lead since HBM2 (2019). TC-NCF (Samsung/Micron historically): thermocompression, die by die, with non-conductive film — slower, more controlled. From HBM4 the contest shifts again: hybrid bonding (Besi leads placements) removes the bumps entirely.
The base die stops being memory and becomes a logic die — made on a foundry node (TSMC for SK hynix; Samsung's own 4nm). So HBM competitiveness is now partly foundry access. And “custom HBM” for NVIDIA/AMD/Google/Amazon raises the bar from “build the JEDEC part” to “co-design with the customer” — a customer-access problem, not only a process problem.
HBM consumes ~3× the wafer area per bit vs DDR5 (TSV keep-out zones, thinning loss, stack-yield compounding; some analysts model ~4× for HBM4 ANALYST). At ~20% of DRAM wafers in 2026 heading to ~30% in 2027 (Samsung EVP via TrendForce), HBM tightens all DRAM supply — and breaks oversupply forecasts built on wafer starts alone.
JEDEC spec = hard; vendor parts exceed spec (Samsung's HBM4 ships at 11.7 Gbps vs JEDEC 8). CXMT's position marked where the reported record puts it.
Huawei's workaround for losing per-chip is system scale: the CloudMatrix 384 puts 384 × Ascend 910C against NVIDIA's 72-chip GB200 NVL72 and wins on aggregate memory (49.2TB vs 13.8TB HBM; ~300 vs ~180 PFLOPS BF16) while paying ~3.9× in power (559kW vs 145kW) ANALYST MODEL — SemiAnalysis. But every one of those 384 chips needs HBM. Move the two variables that matter — when domestic EUV-class patterning arrives, and what CXMT's stacking yield reaches — and see which constraint binds.
TSMC-made dies and Samsung/SK hynix HBM2E inside shipping 910C accelerators — stockpiled or pre-control supply. TSMC attributes its dies to pre-Sept-2020 wafers; Samsung and SK hynix state they have had no Huawei business since 2020. The separate Sophgo route — ~3m TSMC-made dies matching a Sophgo order — became the enforcement case (§06). This is why the HBM clock, not the logic clock, is the near-term binding one: the stockpile is finite.
ASML is only the integrator. Underneath it sit individual monopolies, each hard for a different reason — and the same pattern repeats in HBM, fab equipment, software and materials. Every key below names the holder, its position, the named Chinese challenger opposite it, and the gap. Click a row for the people and patents on the record. Where a person or patent number could not be verified from a public source, the row says so — nothing is filled in from memory.
| Key | Holder | Country | Position | China challenger | Gap |
|---|
Two keys deserve emphasis because they are the least discussed. Lasertec is the sole commercial supplier of actinic (13.5nm) mask inspection — without it, EUV masks cannot be qualified at wavelength, and China has no verified equivalent at all. Hanmi Semiconductor holds ~90% of the TC bonders HBM stacking runs on — the hidden key inside the HBM wall.
One pin per key-holder in the table above — plus the named Chinese challenger opposite it — plotted at its headquarters city. The pattern is the argument: each incumbent key sits in exactly one place (Veldhoven, Oberkochen, San Diego, Yokohama), while China's side is spread across five clusters in ten-plus cities — provincial industrial policy made visible. The furthest-flung pieces are the oldest institutions: Changchun optics and Harbin plasma physics sit roughly 2,500 km from the Shenzhen integration hub that has to combine everyone's parts. Click a pin or a row to match them up.
Map unavailable on this device — the full pin list is beside it.
Pins sit on headquarters cities, not fabs — several holders (Tokyo above all, with thirteen) share one city, so their pins fan out around the city point. Samsung's pin is its Suwon headquarters; SK hynix sits in Icheon, Hanmi in Incheon. Huawei's pin is Shenzhen, with its main campus just up the road in Dongguan.
Short answer: not from Cymer — and the reason generalises. No regime bans “EUV components” in the abstract. A sale is blocked only if it trips one of four screens: (i) an item control (an ECCN/list entry), (ii) the end-use screen (EAR §744.23 — including producing controlled equipment itself), (iii) the end-user screen (Entity List / Footnote-5 — SMIC, Huawei, CXMT-adjacent entities), or (iv) US content/technology (foreign-direct-product and de minimis rules). EAR99 ≠ free for an advanced China fab. And Cymer is a US company: the EAR applies to it directly, not via its Dutch parent — and an LPP source is not a catalogue product anyway; it is bespoke, co-developed, and sold only inside ASML tools. The holes in the fence are the generic versions of the same things.
| Piece | Supplier | Jurisdiction | Rule / regime | Can China buy it? | Workaround actually used |
|---|
Even tools China legally owns need service, spares and software. §744.6 already bars US persons from supporting advanced China fabs, and §744.23 reaches maintenance of controlled equipment. ASML stated (June 2026) it has never delivered a complete EUV system or EUV-specific components to China; DUV sales and service in China continue under licence.
The MATCH Act — introduced 2 Apr 2026, bipartisan — would ban all immersion-DUV sales to China and license or prohibit servicing, spares and software for SMIC, Huawei, CXMT, Hua Hong and YMTC; BofA estimates −14–15% of ASML revenue if fully enacted. Status at 15 Oct 2026: passed the House Foreign Affairs Committee only — it is a bill, not law. ASML's CFO publicly opposed DUV limits on 14 Oct 2026 (Reuters).
Sophgo/TSMC/Huawei: ~3m TSMC-made chips matching a Sophgo order likely reached Huawei's 910B (TechInsights); potential TSMC penalty >$1bn; Sophgo was entity-listed Jan 2025. Lui/Earthmade: a DOJ indictment unsealed 2 Oct 2026 alleges >$300m of NVIDIA servers routed via Malaysia/Singapore to a Hangzhou buyer, 2023–Aug 2026 — allegations, not a conviction.
The legal workaround that worked: stockpiling. China held ~343 immersion DUV tools by early 2026 (~270 of them NXT:1980i class), with >$13bn bought in 2024–25 (CTS via SCMP/TrendForce REPORTED) — bought while licences were still being granted, case by case.
July 2023: gallium/germanium licensing → late 2023: graphite permits + a rare-earth technology export ban → Dec 2024: US-specific Ga/Ge/antimony ban → Apr 2025: rare-earth licensing expansion → Nov 2025: suspension of the 2024 US ban until 27 Nov 2026 (reported). Project Blue estimates China at 98.9% of primary gallium and 68.6% of germanium supply (2025); prices ran 9–10× 2023 levels (Reuters, 18 Sept 2026). The fence, in other words, has a gate on both sides. Also in Oct 2026: Commerce revoked Samsung/SK hynix VEU authorisations for their China fabs — licences for existing operations, not expected for expansion (Reuters, 15 Oct 2026).
Sindlhauser Materials (REPORTED, Bloomberg 14 Oct 2026): in July 2026 China placed this Bavarian coatings and precision-parts supplier inside ASML's supply chain on its export-control list, with 13 other European firms, in retaliation for the EU's 21st Russia sanctions package. The firm depends entirely on Chinese rare earths and critical minerals and reportedly faces shutdown within months. The EU is negotiating a one-for-one swap — delisting an unnamed Chinese firm sanctioned over Russia in exchange for Sindlhauser's relief; EU delisting requires unanimity. The mechanism has two layers of different grades: the licensing regime's data demands (end-customer identities, material usage, photographs of final products) are documented rules; Bloomberg's officials say Beijing used eighteen months of those applications to map Western supply chains before choosing its target — that mapping claim is REPORTED, not documented. Context: yttrium has been under Chinese licensing since Announcement No. 18 (April 2025); Argus pricing put European yttrium oxide at roughly $6/kg in January 2025 and $220–320/kg by late 2025.
MOFCOM and the Ministry of Science and Technology, Announcement No. 48 of 2026 (16 Oct 2026), propose adding 40 technologies (AI 23, biopharma 5, photovoltaics 12) to China's Catalogue of Technologies Prohibited and Restricted from Export. Comment period to 15 Nov 2026 — but an interim registration regime is effective immediately: selling, licensing abroad, or ceding foreign control of any listed technology requires prior registration on MOFCOM's platform. Published/open-source technology is excluded. Three entries fence China's own leads: 266506X (restricted) — AI chip-design technology, including 3D NAND design using bonding technology and DRAM design using bonding or multilayer stacking: the Xtacking and stacking techniques named by method. 266507X (restricted) — AI compute-cluster technology: interconnect ≥800 GB/s, distributed-training fault tolerance, multi-vendor scheduling in clusters over 10,000 accelerator cards: SuperPoD-class know-how. 266504X (restricted) — the core technology of frontier models (weights, checkpoints, source code, architecture) at ≥10^26 FLOPs training compute, ≥2 trillion parameters, or top-ten global capability; models trained on 'core data' and offered as a service are prohibited outright (266501J). Source: https://www.mofcom.gov.cn/zwgk/zcfb/art/2026/art_0a31a3c9ac404f7a9b0e917ce3412997.html
This is the map the thesis is about. Read it bottom to top: China's counter-keys sit at the bottom (materials it controls), the two walls sit in the middle (lithography, HBM), and the demand flywheel sits at the top. On every layer, the Western holder and the Chinese position are named side by side.
Big Fund Phase I ¥138.7bn (2014), Phase II ¥204.1bn (2019), Phase III ¥344bn (~$47.5bn) registered 24 May 2024 — Ministry of Finance the largest holder (17%), operations from 31 Dec 2024, first ~¥93bn toward equipment and materials, with Phase III's focus on lithography and EDA chokepoints. Alongside it, Huawei Hubble has made 60+ semiconductor investments since 2019 across equipment, materials, EDA and design.
On 23 May 2025 BIS letters imposed licence requirements on Synopsys, Cadence and Siemens EDA sales to China (ECCNs 3D991/3E991) HARD — Cadence 8-K. They were rescinded effective 2 July 2025 in a trade framework linked to rare-earth approvals. Separately, Cadence's July 2025 guilty plea over sales to China's National University of Defense Technology via a front company (>$140m in penalties) shows enforcement working even when headline rules reverse.
DeepSeek, Qwen, Kimi and GLM publish open weights. That converts “second-best chips” into deployed compute today: domestic datacentres can extract useful work from Ascend-class silicon, which funds more silicon, which funds more learning. It is the demand-side reason China's catch-up doesn't need NVIDIA parity to compound — and why CANN vs CUDA, not any single chip, is the real software contest.
Frame it as a teardown: if you had to rebuild this from nothing, in what order, piece by piece — and where do you get stuck? Both bills of materials below are in dependency order, because you cannot test a Zeiss-class mirror without the metrology to measure it, and you cannot qualify HBM without an interposer, a tester and a customer chip waiting for it. Patents, papers and teardowns reveal architecture, tolerances and materials choices. They do not reveal coating-run recipes, collector-lifetime management, resist formulations at production purity, or bonding yield recipes — that residue is where iteration volume has to take over.
| Piece | Monopolist | China challenger | Status today | Plausible path | Earliest credible date |
|---|
Overall, three pieces must hit spec simultaneously before a single functional chip exists: optics × source power × actinic metrology. Watch for: independently witnessed source power (watts at intermediate focus) and conversion efficiency; CIOMP measured (not simulated) wavefront/reflectivity publications; any Chinese actinic mask-inspection prototype; a named-fab installation of a domestic advanced scanner; HHCK GMC capacity expansions; CXMT prospectus language adding an HBM line item; named-customer HBM3E qualification announcements.
What shifts the clocks ±2 years: EUV pulls in only if ≥100W domestic source and CIOMP optics at published spec arrive together; it pushes out if the MATCH Act is enacted (cutting the DUV learning fleet's service life) or optics stay prototype-grade past 2028. HBM pulls in on a named hyperscaler HBM3E qualification in 2027 plus a domestic TC bonder at Hanmi-class throughput; it pushes out if bonder/tester controls extend, or stack yields stall below 40% at 12-high.
The claim under test: moats that rely on know-how dissolve — people move, vendors leak, iteration volume teaches. The record supports a sharper version. Know-how moats dissolve at a rate proportional to (people mobility × iteration volume) and inversely to the number of independent monopolies that must be replicated simultaneously. HBM has few enough keys that the moat is visibly dissolving. EUV has roughly a dozen keys that must all turn at once — not one wall but a combination lock — which is why the EUV clock sits ~4 years behind the HBM clock in the base case.
Where it leaked at human speed: ex-Samsung manager Jeon was sentenced to 7 years for leaking 18nm DRAM technology to CXMT — including a hand-copied ~600-step Process Recipe Plan that Samsung R&D valued at ₩1.6tn (~$1.2bn); ex-executive Kim was indicted in Jan 2024 for recruiting Samsung staff to CXMT from 2016 REPORTED — Korean courts. Where it held: Zeiss's moat is not a secret but a network — coating machines, metrology machines, supplier tiers, ASML co-development — renewed every generation. And note the human consequence of the §744.6 US-persons rule: AMEC founder Gerald Yin relinquished US citizenship for Chinese nationality (per AMEC's 2024 annual report, reported by Caixin, Jan 2026).
Everything above is catch-up: closing a measured gap on a road the West already paved. This section asks the different question — where is China doing something uniquely its own that could let it skip a Western generation, or pass the West outright? The honest answer has three tiers: two leapfrogs already proven, one system-level leapfrog in production, and a long tail of credible-but-unproven architectural bets — plus a debunk fence, because several celebrated “breakthroughs” do not survive inspection. Every bet carries its falsifiable signpost: the event that would prove it. And none of this moves the countdown clocks today — a clock moves on high-volume evidence; a fired signpost is what would pull one in.
“Surpass potential” reads: High = a plausible route to being ahead of the West on that route if the signpost fires · Medium = a differentiated, competitive position, with the West moving too · Low = interesting science or a niche, no credible path to a lead in the window.
| Area | Chinese innovator (named) | Western position | Surpass potential | Earliest impact | Confidence |
|---|
These are not inventions. They are why the bets above have different expected values in China. China generated more than twice the US's electricity in 2024 and added more generation in 2010–24 than the rest of the world combined; some Chinese data centres secure ~3 US cents/kWh on long-term contracts vs 7–9 cents in Northern Virginia REPORTED, and SemiAnalysis put parts of China near $56/MWh in early 2025, down from ~$91/MWh in 2022.
So designs that trade power for scarce-node performance — CloudMatrix's ~4× power draw, SSMB's facility overhead, DUV multipatterning's extra steps — are rational in China and irrational in Virginia. Caveat: reported Chinese data-centre utilisation is low (20–30% in some coverage) and provincial grid fragmentation is real — abundance is not efficiency.
The home market is big enough that a Huawei/China standard never needs foreign adoption to reach scale: UnifiedBus, HiBL/HiZQ and ACC chiplets can be mandated into state clouds, telecoms and SOE procurement and still amortise — while the Western analogues (UALink, UCIe, JEDEC HBM) require consensus among rivals: slower, but globally portable. The risk has a name: TD-SCDMA, China's 3G standard — national scale, global dead end (though the learning fed 4G/5G strength). The signpost separating a 5G-style outcome from a TD-SCDMA outcome is voluntary foreign adoption — and one reported data point exists: Samsung's reported Xtacking licence, single-source and unconfirmed, so it does not yet separate the two outcomes.
Underneath both: domestic equipment firms iterating inside a captive fab base that must buy domestic — Naura, AMEC, ACM and peers posted ~37% average 2024 revenue growth vs ~3% for non-Chinese peers REPORTED. A catch-up multiplier more than a leapfrog — except where domestic memory champions pull suppliers (extreme-aspect-ratio etch, for one) to the frontier with them.
The Science Advances result is a ferroelectric FET whose gate electrode was scaled to 1nm physical length, running at 0.6V with very low switching energy — excellent FeFET / memory-device science HARD — the paper. It is not a 1nm logic node, not a general-purpose transistor at 1nm design rules, and not a chip. The headline is a category error.
Tsinghua's Taichi / Taichi-II (Science 2024) and LightGen (SJTU/Tsinghua, Science Dec 2025) are real, strong papers. The multiples are system-level estimates for narrow analog/optical workloads — small-dataset classification, Ising/optimisation, constrained generation — excluding the electronic control, memory, data conversion and programmability a GPU provides. Even sympathetic follow-up coverage concedes such chips cannot run general programs or replace GPUs.
No primary, official or reputable-press corroboration found. The verifiable record is a 2023 site-selection visit and a plan, with Tsinghua itself saying a solid research device still had to be built and there was “a long way to go.” This page does not map it and does not date it FORUM SPECULATION.
Both trace to one December 2025 syndicated article series, republished across financial-content farms, with details that mutate between republications and no named primary source. The reputable version — Reuters — says the opposite on the key point: prototype testing, no working chips yet, 2028 production goal.
The $5.57M figure is the marginal GPU-rental cost of the final training run only, implied by the V3 paper's 2.788M H800 GPU-hours — excluding prior R&D, data, staff and failed runs. The efficiency lead is real; the $5.6M-as-total-cost meme is not.
Titles attached to the (real) Fudan WUJI work and a reported 8-inch 2D pilot line. WUJI runs at kHz-class clocks with 5,900 transistors; no source supports any performance comparison with a 2nm product — and the pilot-line claim itself is unverified in this pass.
Verdict of the evidence: China's leapfrog case is real but narrow. Two leads are already banked — YMTC's bonding architecture, which Samsung is reported to have licensed (unconfirmed), and an open-weight efficiency stack the West itself builds on. One system-level lead (SuperPoD scale) is in production today and pays for it in watts. Everything beyond that is a bet with a named signpost and a date: the Kirin 2026 teardown (months), CXMT's 4F² RDIMM (about a year), the Atlas 950 in production (2027), SSMB's multi-turn trapping (a decade). And the shape matters for the thesis: the proven leapfrogs live in architecture, bonding, systems and algorithms — the layers sanctions cannot easily reach — not in the physics-bound layers (optics, sources) where the clocks still rule.
Drag the year. Everything up to your marker is the record — controls landing, prototypes, qualifications, IPOs. Beyond today, the markers are the clock milestones from §15 of the dossier: estimates, graded as such, not events.
Three charts, each with its grading attached. Where two reputable sources conflict, both are shown — merging them would be the dishonest move.
CXMT vs the three HBM makers. CXMT ~350k wpm is a SemiAnalysis estimate for end-2026 ANALYST MODEL; comparators as reported 2025–26.
CXMT's IPO (STAR Market, 27 July 2026 HARD): ¥8.66 offer, raised ¥57.92bn (~$8.6bn) — the largest mainland semiconductor IPO on record — debut close ~¥49 (+466%), market cap ~¥3.31tn. The prospectus allocates ¥13bn to DRAM upgrades, ¥9bn to next-gen DRAM R&D, ¥7.5bn to wafer-line upgrades and ~¥28bn to working capital — and contains no dedicated HBM project line item. Morningstar: fair value ¥14.90, no moat.
CSIA via TrendForce (12 Jan 2026): adoption in new Chinese fab lines. Yole (June 2026): localisation share. Different denominators — shown side by side, not merged.
Also reported: an unwritten ~50% domestic-equipment expectation attached to new fab approvals REPORTED, secondary. Etch is China's strongest big-tool position — AMEC claims 5nm-class etch in TSMC validation, and domestic adoption in etch/deposition exceeds 40%; lithography, at 18%, is the weakest — which is the whole story of this page in one bar.
Made in China 2025 targeted 70%. What was achieved depends entirely on the definition: IC Insights-style measures (ICs produced in China as % of China's IC market) give ~19.4% for 2025, with China-HQ firms only ~6–10% of that; other expert estimates run ~30%, some commentary ~40% of consumption. Foreign fabs in China in or out, value vs units — that is the whole spread.
Micron's CEO sees shortage through 2027–28 with >75% of FY2027 output committed; Intel's CEO sees “no relief until 2028”; TrendForce has conventional DRAM contract prices +10–15% QoQ in Q4 2026. Against that runs the classic memory-cycle argument (aired by Jen Zhu Scott, Musk and Korean columns this month): scarcity → profit → production → price war → oversupply in 18–24 months — implying a commodity-DRAM glut risk in 2028–29, precisely because CXMT and the majors are all adding commodity capacity at once, while HBM stays tight because its constraint is packaging, test and customer qualification, not wafer starts. The ~3× wafer-area math is why both can be true at once.
HBM market-size forecasts for 2030 diverge by house; this page anchors on the robust numbers instead — wafer share (~20% of DRAM wafers in 2026 → ~30% in 2027) and maker shares (SK hynix ~62% of HBM shipments Q2 2025 / 57% of revenue Q3 2025, Counterpoint).
Message boards and analyst threads are part of the information ecosystem — and they are bullish well beyond the reported record. Everything in the dashed zone below is MESSAGE-BOARD / FORUM SPECULATION: summarised so you can see what is being claimed, and fenced so it can never be mistaken for the record above. None of it feeds the countdown clocks.
Boards repeatedly claim a domestic EUV tool is already patterning test wafers at a Huawei/SMIC site. Corroboration: none in reputable reporting — Reuters' account (light, no chips) is the ceiling of the verified record.
Circulate via syndicated, low-quality reposts, loosely attributed to Harbin / Huawei Dongguan. Corroboration: none — no peer-reviewed power figure exists.
Wafer-start figures above and below the ~350k wpm estimate, “HBM yield” percentages with no methodology, imminent NVIDIA-scale qualifications. The sourced record is: samples H2 2025, HBM3E risk production Sept 2026, ~25% 8-high yield as a SemiAnalysis model. Everything beyond that is speculation.
Forum estimates of stockpiled Samsung/SK hynix HBM vary by an order of magnitude. Only the existence of HBM2E from both makers inside teardowns is reported; no verified volume exists publicly.
“~65% Chinese mirror reflectivity vs Zeiss ~70%”, “Huazhuo is the second stage maker after ASML”, “a >1kW SSMB source is already built at Xiong'an”, JCET as “exclusive SK hynix HBM3E packaging partner at 98.5% yield”. All unverified — the JCET claim in particular should not be used.
English-language boards skew sceptical-on-EUV / bullish-on-HBM-timelines; Chinese-platform discussion, as relayed, skews the reverse; Korean columns skew toward leak and talent anxiety; Dutch trade press focuses on ASML supplier strain and MATCH Act risk.
The full bench: every company and institution in the dossier, with its country, layer and role. Search it.
| # | Company / institution | Country | Layer | Role / note |
|---|
The load-bearing claims with their grades, the questions the research could not close — stated plainly rather than filled in — and the source list.
| Claim | Grade | Basis |
|---|
The full report — every table intact: the three clocks with base/bull/bear and their basis, the piece-by-piece roadmap, the Keys roster with people and patents, the purchasability map, the HBM teardown, the ecosystem map and the graded claims — as one Markdown file, structured to drop straight into Claude, ChatGPT or any other model and ask it to find the holes.
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